Wire bonds, physically, as well as electrically, connected to underlying circuitry, of semiconductor chips, are used to connect the specific semiconductor chip to packaging elements, such as printed circuit board, or ceramic modules. Bond pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bond pads are required to transmit power/ground and input/output signals to the chip devices. It is thus important that reliability of bond pad should be sufficiently high to ensure the life time of the device. The general bond pad consists of metal layers separated by inter-metal dielectric (IMD) layers and metal vias passing the IMD layers for electrically connecting the metal layers. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection. Wires are bonded to the bond pad and to the chip package forming electrical connections between the chip and the package.
In most cases metal vias are patterned as an array of grids in the IMD layer underlying an uppermost metal layer. The large, exposed, surface area of IMD layer, however, surrounding the smaller regions of metal vias, can result in defect formation, as a result of the large bonding force experienced during the wire bonding tests, where the large bonding force is distributed throughout the overlying bond pad. A significant failure mode involves cracking of the IMD layer. Once a small crack is initiated to propagate along the IMD layer, under stresses it will grow extensively during subsequent processes. One approach for eliminating the cracks, the top metal via is designed as a mesh pattern. Such a mesh via pattern is often formed or deposited in a manner that can't fully fill holes to provide poor coverage on intersection areas where line vias cross with each other, mainly because of a marginal photolithography process window induced by circuits under pad (CUP) layout. This impacts reliability, bondability and quality control (QC) results, and the yield impact may reach 10˜15% depending on variations in chip size. In order to avoid problems in devices that could arise from non-fully filled metal vias, design rules do not allow integrated circuits to underlie the bond pad.
The adhesion between the metal via and the IMD layer is also poor while the bonding wires are bonded to the bond pads by thermal compression, so that the bonding pads often peel off and the IMD layers often crack. FIG. 1 is a top view illustrating one approach for improving adhesion and solving the peeling issue. The metal vias 12, 14 and 16 formed in alternating IMD layers 10 are arranged in tetraskelion respectively, so that a compressive mechanical stress from any direction of the substrate can be released. Taking the top metal vias 12 as an example, each metal via 12a in the vertical-via pair is staggered and parallel to each other, and each metal via 12b in the horizontal-via pair is staggered and parallel to each other. However, the IMD layer 10 is a brittle oxide layer and a straight open space (as indicated by the dotted lines 13a and 13b) is existed between the vertical-via pair and the horizontal-via pair. There is one potential concern that the IMD oxide layer may propagate straightly along the space 13a or 13b. FIG. 2 is a top view illustrating another approach for improving adhesion and solving the peeling issue. The top via pattern in a top-level IMD layer 20 is arranged in an array including via groups 22 and 24. The parallel lines vias 22a, 22b and 22c in the first via group 22 and the parallel line vias 24a, 24b and 24c in the second via group 24 extend in different directions without generating an intersection area there between, which avoids poor via coverage. However, a straight open space, as indicated by the dotted lines 23 and 25, is existed along the domain boundary between the two adjacent via groups 22 and 24. There is one potential concern that the brittle IMD layer 20 may propagate straightly along the space 23 or 25.